Reverse engineering a PCB typically runs $300 to $800 for a 2-layer board, $800 to $2,500 for 4 layers, and $2,500 to $8,000+ for 8-layer and HDI designs, with turnaround from 5 business days to 6 weeks. Board size, via types, firmware recovery, BOM obsolescence and IPC-A-610 Class 3 or ISO 13485 documentation explain most of the spread.
What You Are Actually Paying For
When an engineering partner quotes printed circuit board reverse engineering, the quote covers engineering time, not a product. The deliverable is a complete manufacturing data package — Gerber files, drill files, a reconstructed schematic, a verified netlist, a bill of materials and test evidence — rebuilt from physical samples of a board whose original design files no longer exist. Every price is therefore a function of labor hours across five workstreams, and every variable that changes those hours changes the number.
In our lab, a representative 4-layer industrial control board consumes 25 to 40 engineering hours from intake to verified fabrication files. That complexity band is also where most quotations cluster: complex enough to justify outside engineering help, common enough that the workflow is well understood. The table below shows how those hours distribute in a typical recovery project.
| Workstream | What happens | Typical hours, 4-layer board |
|---|---|---|
| Intake and non-destructive inspection | Photography, dimensional measurement, layer-count estimation, coating assessment | 2–4 |
| Scanning, imaging and delayering | High-resolution capture of both surfaces, layer-by-layer removal, inner-layer imaging | 6–10 |
| Netlist and Gerber extraction | Copper trace digitization, via and pad-stack mapping, DRC-clean artwork generation | 8–14 |
| BOM reconstruction | Component identification, marking decode, decapsulation where required, obsolete-part cross-referencing | 5–8 |
| Verification and reporting | Netlist comparison, first-article inspection, functional test against the donor board | 4–8 |
Understanding this breakdown is the first step to reading any quotation. A vendor who cannot explain where the hours go cannot explain where the risk sits, either. We issue an itemized scope with every quotation — the same artifact your quality team will want on file under an IEC 62402 obsolescence-management program when the board keeps a production line running. If you are new to the workflow itself, our guide to the five critical steps in reverse engineering a PCB walks through each phase in detail, and the reverse engineering service page describes the full deliverable set.
PCB Reverse Engineering Cost by Layer Count
Layer count is the single largest driver because it multiplies the imaging work. A 2-layer board needs two surface scans and no delayering. A 6-layer board needs four additional inner-layer recoveries, each involving controlled material removal, registration against the scan datum and digitization of artwork no one has seen since the original CAD session. The ranges below reflect typical 2026 market pricing for a complete, verified documentation package.
| Board complexity | Typical NRE range (USD) | Engineering hours | Typical turnaround |
|---|---|---|---|
| 2-layer, through-hole or simple SMT | $300–$800 | 8–15 | 5–8 business days |
| 4-layer, mixed SMD and through-hole | $800–$2,500 | 20–40 | 2–3 weeks |
| 6-layer with blind or buried vias | $1,500–$4,000 | 40–70 | 3–4 weeks |
| 8–10+ layer, HDI, high BGA density | $2,500–$8,000+ | 80–150 | 4–6 weeks |
These figures are one-time non-recurring engineering charges for the files, which become your property and stay valid for every future build. The ranges are wide because layer count sets the floor while the five variables in the next section set the ceiling. Delayering a 6-layer servo-drive board takes our team three to five working days on its own; a board of the same layer count built entirely from 0402 passives under a thick conformal coat can double the extraction hours without the layer count changing at all.
The Five Variables That Move the Price
1. Physical size and copper density
A 200 by 150 mm densely routed backplane is not the same project as a 60 by 40 mm controller card with an identical layer stack. Net and trace count drive digitization time almost linearly: every additional thousand nets adds measurable hours of trace following, and a high-density industrial design can double extraction time versus its layer-count baseline on footprint alone.
2. Via architecture and component packaging
Blind and buried vias cannot be seen from either surface, so mapping them requires cross-sectioning and X-ray confirmation, and each hidden via layer adds an imaging pass. Fine-pitch ball-grid arrays compound the problem by placing their nets beneath the package, which pushes verification toward X-ray and netlist-continuity methods. In our experience a 6-layer board with buried vias and 0.4 mm pitch packaging routinely quotes 50 to 80 percent above a 6-layer board with through-hole vias alone.
3. Firmware and IC-level recovery
If the replacement board must boot, documentation alone is not enough. Microcontroller and memory contents usually need to be read from a donor device, verified and re-associated with the recovered design — work that requires documented proof of ownership and an NDA before any chip is opened. At our lab this adds $200 to $900 for common architectures, and more when the target is a one-time-programmable or house-branded part that needs decapsulation and die-level analysis.
4. Component obsolescence inside the BOM
A bill of materials built from parts with living datasheets is quick to reconstruct. A 1990s board with house-marked ICs, custom hybrids and discontinued relays is a different project: unmarked packages must be decapsulated or electrically characterized, and every end-of-life part needs a form-fit-function replacement qualified. This is where BOM hours quietly become the largest line item — and where an IEC 62402-driven second-source strategy pays for itself on the next failure.
5. Verification depth and compliance scope
IPC-A-610 Class 2 acceptance is the working default for industrial rebuilds. Class 3 tightens workmanship criteria and process evidence, typically adding 15 to 25 percent effort. For medical equipment the documentation package widens to ISO 13485 servicing records and 21 CFR 820 compliance traces, and the change scope should be written to minimize IEC 60601-1-2 requalification exposure — expect 25 to 40 percent over a standard industrial file. Our guide to PCB testing after reverse engineering details what full verification includes and why it is the most cost-effective insurance in the project.
From NRE to Per-Unit: Batch Manufacturing Economics
The recovery fee is paid once. What each replacement board costs afterwards follows ordinary manufacturing economics: fabrication tooling, stencils, assembly programming and components, all amortized across the batch size.
| Batch size | What drives the per-board figure | Typical pattern |
|---|---|---|
| 1–5 units | Tooling and stencils amortized over very few boards; component minimum-order surcharges | Highest per-board figure; tooling of $150–$600 spread across the batch |
| 10–50 units | Tooling fully absorbed; cut-tape and short-reel component pricing becomes available | Per-board figure typically drops 30–50% versus prototype quantity |
| 100+ units | Volume fabrication pricing, full component reels, single assembly setup | Lowest per-board figure; the original NRE approaches zero as a share of lifetime spend |
The practical implication is straightforward: a $1,800 documentation package spread over 100 replacement boards contributes $18 per board, and across a five-year spare-parts program the NRE becomes a rounding error next to the downtime it prevents. This is also the arithmetic behind the case for combining recovery and manufacturing in one partner — when the team that recovers the files also builds the boards, the documentation is generated once, correctly, with manufacturing as the endpoint rather than an afterthought.
Who Owns the Recovered Files — and Other Commercial Terms
Because the output is engineering data rather than a physical product, ownership terms belong in the conversation before the purchase order. At our lab the default is unambiguous: the Gerbers, netlist, schematic and BOM recovered from your board are your property, delivered in native formats, with no license fees on future builds and no lock-in to our fabrication lines. The agreement runs under mutual NDA in both directions — your design stays confidential, and the work is performed only on hardware you own or are documented to service.
Payment structure typically follows the risk profile of the work: a mobilization portion at kickoff and the balance on delivery of verified files, with the verification report serving as acceptance evidence. Two conditions legitimately re-open a fixed quote after inspection: a hidden board revision that differs from the sample photographs, and discovering mid-project that firmware recovery requires a decapsulation step the outside markings did not reveal. A vendor who lists those triggers up front is doing the scoping work the price depends on; silence on re-quote conditions is a warning sign in either direction.
What We Need to Quote Your Board Accurately
Accurate quotation is a documentation exercise on your side too. The single biggest accelerator is supplying two intact samples — one to delayer destructively, one preserved as the golden reference for verification. Beyond that, the inputs below set the scope precisely.
| Input | Why it matters |
|---|---|
| Two intact samples | Delayering is destructive; a second unit anchors verification and protects against a hidden board revision |
| Dimensions and layer count if known | Sets the baseline pricing tier before any lab work begins |
| Power-up requirement | Determines whether firmware and IC-level recovery is in scope |
| Target annual quantity | Sets the NRE amortization and the manufacturing tier |
| Compliance target | IPC-A-610 Class 2 or Class 3, or an ISO 13485 medical documentation package |
| Any surviving records | Even an old assembly drawing PDF can cut BOM reconstruction hours by a third |
With those inputs, an itemized quotation typically returns within one to two business days — priced per workstream, so you can see exactly what each decision adds or removes.
How Customers Keep the Number Down
Three habits consistently reduce project scope. First, send the best sample you have: a clean, uncoated, undamaged board cuts imaging hours dramatically versus a unit that survived ten years in a washdown environment. Second, send everything that survives in the filing cabinet — an old assembly drawing, a test procedure, even photographs of the silkscreen reduce BOM reconstruction effort. Third, hold a minimum-change philosophy: rebuild what failed in form-fit-function and leave working subsystems untouched, because every redesign decision adds verification hours and, in regulated settings, requalification exposure. The most expensive project is rarely the most complex board — it is the ambiguous one, quoted wide because critical facts were missing at intake.
The Bottom Line
PCB reverse engineering in 2026 costs $300 to $800 for a simple 2-layer board, $800 to $2,500 for the 4-layer boards that dominate industrial rebuilds, and $2,500 to $8,000+ at the 8-layer and HDI end — a one-time NRE for files you own, amortized toward zero across every future replacement batch. Board size, via architecture, firmware work, BOM obsolescence and compliance tier explain nearly all of the spread between a low and a high quote on the same board.
Send photographs of both sides, the dimensions and your target quantity through our project evaluation page, and you will receive an itemized quotation, typically within one to two business days.